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Digital ASIC Design Service

Turn Your Digital ASIC Ideas into Silicon Reality

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Our Team

  • Our Digital ASIC Design Team transforms your complex challenges into success stories through end-to end
    solutions.
  • We specialize in design, implementation, and verification of digital ASICs, ranging from enhancement of existing IPs for power and performance improvements, to custom IP development and licensing, all the way to full turnkey packaged and tested silicon.
  • We optimize performance across digital and mixed-signal applications to achieve cost-effective and timely results.
CoreHW Digital ASIC Design Team

Our Expertise

  • We have extensive experience in all the phases needed to design, implement, and verify state-of-the-art digital ASICs.
  • We apply a wide range of optimization techniques throughout the development flow, from architecture conceptualization to place-and-route, to deliver the best possible performance and cost for a given set of constraints.
  • We collaborate with both in-house and external analog/RF design teams. This enables us to co-design, enhance, and verify together the analog and digital parts of a mixed-signal ASIC.
CoreHW digital ASICs

Our Advantages

Co-operation with Analog and RF Design Teams

We work in strong synergy with analog/RF designers, in order to deliver best-in-class integration of advanced digital functionality into complex mixed-signal ASICs.

Digital Enhancement of Analog Chips

We devise digital circuits and control systems that significantly optimize the performance of analog IPs, by exploiting the speed and low cost of integrated digital signal processing.

Comprehensive Mixed-signal Design Verification

We can verify both the analog and digital parts of a mixed-signal ASIC, thus ensuring that the complete system will fulfill its performance requirements under all conditions.

Our Services

System-level architecture and specification

  • Initial project feasibility investigation
  • High-level architecture conception
  • Top- and block-level specification definition
  • Design of advanced digital signal processing (DSP) and control algorithms
  • System-level modeling with Matlab, Simulink, Python

RTL design

  • Development of high-quality RTL from system-level models
  • Code optimizations to improve timing/power/area of arithmetic datapaths
  • Automatic RTL code and documentation generation
  • Hardware description languages: Verilog, SystemVerilog, VHDL

Physical implementation and DFT

  • Floorplanning and design constraints
  • Physical synthesis and place-and-route
  • Sign-off checks: Formal Verification, STA, DRC, LVS, Power Integrity Analysis
  • Integration with analog IPs (analog-on-top, digital-on-top)
  • Design for Testability, ATPG

Advanced IC verification

  • SystemVerilog UVM
  • SystemVerilog Real Number Modeling (RNM) of analog IPs
  • Mixed-signal verification with Verilog-AMS
  • Regression testing
  • Hardware/Software co-verification

Some of Our Projects

Here is a short list of our recent projects.

  • Bluetooth range extender IC (130nm)
  • Low-power RF front-end IC (130nm)
  • Imaging Sensor Readout ASIC (130nm, 180nm)
  • Bluetooth AoA and AoD switch ASIC (130nm)
  • CLKPLL IP for large scale digital SoCs (22nm)
  • Dual PLL chip for RF LO and clock signal generation (40nm)
  • MMW PLL IP for Radar and Telecommunication applications covering multiple frequency ranges (22nm)
  • Analog IP modelling, Top-Level Verification and Post-Silicon Validation for an Automotive Sensor Readout ASIC (130nm)

Some of Our Tools

Cadence

Cadence

Synopsys

Synopsys

In-house tools

In-house tools

Our design flow is enhanced with in-house tools to improve overall productivity and quality.

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