Our Digital ASIC Design Team transforms your complex challenges into success stories through end-to end solutions.
We specialize in design, implementation, and verification of digital ASICs, ranging from enhancement of existing IPs for power and performance improvements, to custom IP development and licensing, all the way to full turnkey packaged and tested silicon.
We optimize performance across digital and mixed-signal applications to achieve cost-effective and timely results.
We have extensive experience in all the phases needed to design, implement, and verify state-of-the-art digital ASICs.
We apply a wide range of optimization techniques throughout the development flow, from architecture conceptualization to place-and-route, to deliver the best possible performance and cost for a given set of constraints.
We collaborate with both in-house and external analog/RF design teams. This enables us to co-design, enhance, and verify together the analog and digital parts of a mixed-signal ASIC.
Co-operation with Analog and RF Design Teams
We work in strong synergy with analog/RF designers, in order to deliver best-in-class integration of advanced digital functionality into complex mixed-signal ASICs.
Digital Enhancement of Analog Chips
We devise digital circuits and control systems that significantly optimize the performance of analog IPs, by exploiting the speed and low cost of integrated digital signal processing.
Comprehensive Mixed-signal Design Verification
We can verify both the analog and digital parts of a mixed-signal ASIC, thus ensuring that the
complete system will fulfill its performance requirements under all conditions.
System-level architecture and specification
Initial project feasibility investigation
High-level architecture conception
Top- and block-level specification definition
Design of advanced digital signal processing (DSP) and control algorithms
System-level modeling with Matlab, Simulink, Python
Development of high-quality RTL from system-level models
Code optimizations to improve timing/power/area of arithmetic datapaths