CoreHW

DCDC Converter & PMIC Design Services

CoreHW develops custom DC-DC converters, LDOs, charge pumps and complete power management ICs—from architecture and system modeling to circuit design, layout, verification, package and PCB analysis, and laboratory validation.

We design fully integrated PMICs and controller-based solutions with discrete power stages, tailored to voltage, current, efficiency and thermal requirements.

We engineer power solutions for high efficiency, low ripple, controlled EMI, fast transient response, robust protection and reliable system integration.

Discuss Your Power IC ProjectExplore Power Management IP
CoreHW power management integrated circuit for DC-DC and PMIC design.

Load current

Integrated PMICs up to 10 A, with driver-based solutions for higher currents

Input voltage

Up to 40 V, higher with specific process nodes

Output voltage

From 0.6 V to 15 V, extendable beyond this range

Process nodes

22–180 nm CMOS, SOI and BCD technologies

POWER THAT FITS THE SYSTEM

Convert, Regulate and Protect Every Power Rail

A DCDC converter changes one DC voltage or current level to another. A power management IC can combine multiple converters with sequencing, monitoring, communication, protection, production-test functions and controlled supply switchover.

CoreHW defines the architecture around the source, load and system requirements—not around a fixed topology. The objective is stable power delivery with the required efficiency, ripple, transient response, EMI performance, silicon area and external-component count.

POWER MANAGEMENT SOLUTIONS

Power Conversion and Regulation Solutions

Efficient Switched-Mode Conversion

Buck, boost and buck-boost converters for step-down, step-up and wide-range power conversion. Buck operates with Vout below Vin, boost with Vout above Vin, and buck-boost can operate on either side of Vin. Switching frequency is selected to balance efficiency, ripple, transient response, EMI and external-component size. Higher switching frequencies can reduce passive-component size but may increase switching losses and EMI challenges. Lower switching frequencies can reduce switching losses but generally require larger inductors and capacitors.

Low-Noise Linear Regulation

PMOS- and NMOS-output LDOs for sensitive analog, RF and mixed-signal supplies. LDOs provide very low noise and no switching RF emissions during continuous operation, but efficiency decreases as Vin–Vout increases because the voltage difference is dissipated as heat. PMOS outputs support lower-dropout operation, while NMOS outputs require more voltage headroom.

Scalable Power Architectures

Single-phase, multiphase, coupled-inductor multiphase and single-inductor multiple-output solutions for higher power or multiple rails. Multiple converter phases can combine output power but require precise timing to prevent unwanted current between individual converters. SIMO architectures can share one inductor across several rails at the cost of more complex digital control.

Control, Monitoring and Protection

Power sequencing, SPI or I2C/SMBus/PMBus connectivity, UVLO, OVLO, overcurrent, short-circuit and thermal protection. Production-test functions, status alarms and controlled switchover between supplies can also support reliable system operation.

WHY COREHW

One Engineering Team from Requirements to Measured Silicon

Architecture Selection

CoreHW balances voltage range, load profile, efficiency, ripple, transient response, noise, EMI, die area, package limitations and external components. Architecture selection also considers the relationship between Vin and Vout and the acceptable number and range of external components.

Custom Design Plus Reusable IP

DCDC, LDO, reference, bias, sensor, data-converter, interface and protection blocks can support a faster, lower-risk implementation. Reusable IP and full-chip design experience is available across several process nodes, including 180 nm, 130 nm and 22 nm.

Parasitic-Aware Physical Design

High-current and high-voltage design, ESD and latch-up protection, power-transistor layout, floorplanning, pad planning and package selection are addressed early. Package, bond-interconnect and PCB parasitics are included where applicable to the electrical specification.

Verification and Validation

System models, PVT and Monte Carlo simulation, extracted post-layout verification, package and PCB modeling, automated reporting and laboratory measurements create a traceable design flow. Compliance matrices compare required limits with simulated and measured results.

CAPABILITY OVERVIEW

CoreHW Power Management Capabilities

CoreHW power management capabilities by design area
AreaRepresentative Design Capabilities
ArchitecturesLDO, buck, boost, buck-boost, single-phase, multiphase and multi-output
Load currentBelow 100 mA to 10 A
Input voltageDesign experience up to 16 V
Output voltage0.6–5.5 V; up to 15 V with suitable specialized processes
Switching frequencyRepresentative custom-design range of 500 kHz–2 MHz

ARCHITECTURE OPTIONS

Select the Right Converter for the Rail

Power converter architecture options and trade-offs
ArchitectureBest fitMain trade-off
LDOClean analog or RF supplies where Vin is close to Vout. PMOS-output LDOs support lower-dropout operation, while NMOS-output regulators require more voltage headroom.Lowest switching noise, but efficiency decreases as Vin–Vout increases. LDOs also avoid switching RF emissions during continuous operation.
BuckEfficient step-down conversion and higher load currentRequires an inductor and careful switching-noise control
BoostStep-up conversion where Vout must exceed VinOutput current is lower than input current; protection is critical
Buck-boostRails that can be above, below or negative relative to VinFlexible, but control near Vout ≈ Vin is more complex
Multiphase, coupled-inductor multiphase or SIMOHigher output power or several output rails. Multiple phases can combine output power, while SIMO can share one inductor across several rails.Precise timing and digital control are essential. Timing must prevent unwanted current between phases, while SIMO requires more complex control of the shared inductor.
Charge pumpLow- to moderate-current applications requiring VOUT above VIN or a negative voltage rail, where an inductorless solution is preferred.Limited output-current capability

Switched-mode converters generally require an inductor and input/output capacitors. Higher switching frequency can reduce ripple but increases switching losses and EMI design demands.

CHALLENGING POWER IC DESIGN

Design Challenges We Solve

  1. 01

    Efficiency Versus EMI

    Switching frequency, edge rate, dead time, gate drive and power-stage sizing are optimized together. Lower emissions and lower switching losses require a deliberate system-level balance. Slower switching edges can improve the emission spectrum but increase transition losses, creating a direct EMC-versus-efficiency trade-off.

  2. 02

    Ripple and Transient Response

    Control architecture, loop behavior and manufacturer models for external inductors and capacitors are used to meet voltage-quality and load-step targets. External-component count and acceptable component ranges are considered as part of the system-level design.

  3. 03

    Noise Coupling and Isolation

    Shielding, guard rings, physical separation, dedicated supply paths and disciplined routing protect sensitive bias and analog nodes from switching activity. Depending on sensitivity, CoreHW can also use VDD/VSS pseudo-shielding, well-contacted substrate and N-well guard rings, increased separation and dedicated power pads.

  4. 04

    Current, Heat and Package Parasitics

    Power-device geometry, short current paths, dense vias, multiple pads and early floorplanning reduce IR drop, current crowding and hot spots. Package and bond-interconnect resistance, inductance, capacitance and mutual coupling are included in the design model. Supply routing and top-level floorplanning are planned early, and package parasitics are checked for unwanted transient oscillation.

  5. 05

    Protection and Fault Handling

    Thermal shutdown, overcurrent protection, short-circuit protection, UVLO, OVLO, alarm signaling and controlled supply switchover can be integrated according to the system specification. Thermal protection can include programmable thresholds and hysteresis, with alarm handling defined by the system specification.

  6. 06

    Matching and Layout Symmetry

    Precision ratio-based structures use matched unit devices, symmetric routing, dummy elements and controlled metal fill to preserve intended matching and layout symmetry. These methods help protect sensitive analog performance from systematic layout effects.

TOP-DOWN ENGINEERING

CoreHW DCDC and PMIC Design Methodology

  1. System modeling

    Simplis, Octave and Verilog-A models define block requirements and support early PCB and laboratory-test planning. The system model also compares architecture options and enables PCB and test-hardware development before transistor-level design is complete. The system-level model serves as a simulatable specification throughout the whole design process.

  2. Circuit and control design

    Power stages, drivers, references, protection, sequencing, monitoring, interfaces and digital control are checked against the system-level model and simulatable specification.

  3. Robustness verification

    Designs are evaluated across applicable PVT combinations, followed by Monte Carlo analysis and a specification-to-results compliance matrix. PVT covers process, supply voltage and temperature, while Monte Carlo evaluates statistical lot-to-lot and device-mismatch variation.

  4. Physical implementation

    DRC, LVS, parasitic extraction and post-layout simulation address crosstalk, IR drop, device matching, thermal behavior and routing efficiency. Extracted layout parasitics are back-annotated into post-layout simulations to verify the implemented design against the schematic model.

  5. System and silicon validation

    Package, bonding, PCB traces and external-component SPICE models are included. Test hardware, chip wake-up, automated measurements and reporting complete the flow. Manufacturer models are used from the beginning, PCB trace parasitics can be estimated or extracted, and compliance reporting supports customer documentation.

Cadence and Synopsys design environments, Simplis, and other industry-standard tools support modeling, implementation and sign-off. Relevant process experience spans 22 nm, 130 nm and 180 nm CMOS, BCD and SOI technologies. Projects can be aligned with applicable ISO 26262 and customer-specified IEC or JESD requirements.

PROVEN POWER MANAGEMENT WORK

DC-DC Design Experience and Reusable IP

CoreHW’s power-management experience spans low-power analog and SMPS designs through multi-amp implementations up to 10 A, including reusable IP, customized blocks and full-chip projects.

500 mA Buck DCDC IP

A programmable TSMC 180 nm BCD platform for low-power power management applications. It demonstrates CoreHW’s reusable-IP approach for compact, lower-current power solutions.

View IP

5 A Buck DCDC IP

A TSMC 180 nm BCD constant-on-time switching regulator with a 4.25–15 V input range and scalable single- or multiphase integration. It demonstrates scalable higher-current design across single- and multiphase implementations.

View IP

Automotive, Telecom and HPC Projects

CoreHW references include buck and boost converters, LDOs, charge pumps, drivers, and 500 mA to 5 A single- and dual-phase DCDC implementations. CoreHW’s broader power-management design experience extends to 10 A. (CoreHW)

APPLICATIONS

Power IC Design for Demanding Electronic Systems

Consumer and portable electronics with low-power wireless connectivity.

Consumer and Portable

Low-current rails, low standby power, compact external components and longer battery operation. Digitally controlled power-saving modes can further reduce standby current and extend battery life in portable systems.

Automotive electronics and mixed-signal ASIC systems.

Automotive

Wide-temperature, protected and standards-aware power management for sensors, controllers and mixed-signal ASICs. Integrated monitoring and fault protection support reliable operation across demanding automotive conditions.

Telecommunications and high-performance computing infrastructure.

Telecom, AI and HPC

Efficient higher-current rails, multiphase operation, accurate monitoring and package-aware power delivery. Scalable multiphase architectures support high-output, reliable supply rails for telecom, AI and data-center systems.

Industrial and quantum-control electronics for precision measurement systems.

Industrial and Quantum-Control Electronics

Stable, precise and fast supplies for sensitive control, measurement and mixed-signal systems. Low-power SMPS options can reduce cooling needs, while robust protection supports reliable industrial and quantum-control operation.

DELIVERABLES AND ENGAGEMENT

From Feasibility Study to Production-Ready Design

CoreHW can provide, for example but not limited to, the following deliverables depending on project scope:

Pre-silicon design and verification

Architecture studies, behavioral models, schematics, simulation environments, digital control, layout and GDSII, DRC/LVS evidence, extracted verification, and integration views.

Testing, validation and productization

Compliance reports, test hardware, measurement reports, and tape-out or productization support.

Additional project deliverables

Package and PCB parasitic models, manufacturer SPICE models for external components, specification-to-results compliance matrices, automated simulation reports, and early test-hardware planning.

Engagements can cover selected design blocks, IP customization or licensing, a complete PMIC, or a turnkey ASIC program. Fixed-NRE and time-and-material models are available.

FAQ

DCDC Converter and PMIC Design Questions

CoreHW supports linear, switched-mode, single-phase, multiphase, coupled-inductor multiphase and multi-output power architectures, including the required control, monitoring and protection.

START YOUR POWER IC PROJECT

Design the Right Power Architecture

Share your voltage, current, efficiency, noise and integration requirements. CoreHW can define the right DCDC or PMIC architecture and implementation path.

Discuss Your DCDC or PMIC ProjectExplore Power Management IP